Field-Programmable Gate Arrays (FPGAs) are increasingly shaping the future of network security, thanks to their flexibility, parallel processing capabilities, and energy efficiency. In this survey, we examine 50 peer-reviewed studies published between 2020 and 2025, selected from an initial pool of 210 articles based on relevance, hardware implementation, and the presence of empirical performance data. These studies encompass a broad range of topics, including cryptographic acceleration, intrusion detection and prevention systems (IDS/IPS), hardware firewalls, and emerging strategies that incorporate artificial intelligence (AI) and post-quantum cryptography (PQC). Our review focuses on five major application areas: cryptographic acceleration, intrusion detection and prevention systems (IDS/IPS), hardware firewalls, and emerging strategies involving artificial intelligence (AI) and post-quantum cryptography (PQC). We propose a structured taxonomy that organises the field by technical domain and challenge, and compare solutions in terms of scalability, resource usage, and real-world performance. Beyond summarising current advances, we explore ongoing limitations—such as hardware constraints, integration complexity, and the lack of standard benchmarking. We also outline future research directions, including low-power cryptographic designs, FPGA–AI collaboration for detecting zero-day attacks, and efficient PQC implementations. This survey aims to offer both a clear overview of recent progress and a valuable roadmap for researchers and engineers working toward secure, high-performance FPGA-based systems.

As the demand for secure communication and data integrity in embedded and networked systems continues to grow, there is an increasing need for cryptographic solutions that provide robust security while efficiently using energy and hardware resources. Although software-based implementations of SHA-3 provide design flexibility, they often struggle to meet the performance and power limitations of constrained environments. This study introduces a hardware-accelerated SHA-3 solution tailored for the Xilinx Artix-7 FPGA. The architecture includes a fully pipelined Keccak-f [1600] core and incorporates design strategies such as selective loop unrolling, clock gating, and pipeline balancing to enhance overall efficiency. Developed in VHDL and synthesised using Vivado 2024.2.2, the design achieves a throughput of 1.35 Gbps at 210 MHz, with a power consumption of 0.94 W—yielding an energy efficiency of 1.44 Gbps/W. Validation using NIST SHA-3 vectors confirms its reliable performance, making it a promising candidate for secure embedded systems, including IoT platforms, edge devices, and real-time authentication applications.