A test model for hardware and software
Publication Name: Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing Prdc
Publication Date: 2011-12-01
Volume: Unknown
Issue: Unknown
Page Range: 292-293
Description:
The paper presents a unified test model which is a mapping scheme for describing the one-to-one correspondence between the input and output domains of a given hardware or software system. Here the test inputs and the fault classes are also involved. The test model incorporates both the verification and the validation schemes for the hardware and software. © 2011 IEEE.
Open Access: Yes
DOI: 10.1109/PRDC.2011.41
