P. Keresztes

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Publications - 3

Training electrical engineers on asynchronous logic circuits based on constant weight codes

Gábor Rózsa A. Nagy P. Keresztes L. T. Koczy

Publication Name: IEEE AFRICON Conference

Publication Date: 2011-12-12

Volume: Unknown

Issue: Unknown

Page Range: Unknown

Description:

The paper introduces a new way for teaching of delay insensitive asynchronous logic circuits. The studies start on high level models, which are VHDL implementations of Dennis-type static dataflow systems. Investigating the operation of the concurrent processes of these models, the main elements of the delay insensitive systems can be derived. Introducing constant weight 'm-of-n' codes immediately at the beginning of the course leads to a proper generalization. So the well known dual-rail code circuits can be considered as special cases of the constant weight code delay insensitive circuits. The paper presents briefly the design practice sessions for students. © 2011 IEEE.

Open Access: Yes

DOI: 10.1109/AFRCON.2011.6072041

Enhanced emulated digital CNN-UM (CASTLE) arithmetic cores

P. Keresztes T. Hidvégi P. Szolgay

Publication Name: Journal of Circuits Systems and Computers

Publication Date: 2003-12-01

Volume: 12

Issue: 6

Page Range: 711-738

Description:

An emulated digital CNN-UM (CASTLE) architecture was published few years ago.1 Different emulated digital CNN-UM architectures are analyzed in the paper. These new modified architectures are optimized according to the silicon area, operating speed or dissipated power. A reconfigurable arithmetic core will also be shown in the paper, by which solution of the neighborhood size can be changed. An advanced CASTLE with pipe-lining is presented. The operation frequency is increased by using this solution in approximately 10 times.

Open Access: Yes

DOI: 10.1142/S0218126603001136

An accelerated digital CNN-UM (CASTLE) architecture by using the pipe-line technique

P. Keresztes T. Hidvégi P. Szolgay

Publication Name: Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

Publication Date: 2002-01-01

Volume: 2002-January

Issue: Unknown

Page Range: 355-362

Description:

Different CNN-UM architecture implementations, analog and emulated digital, were developed. The emulated digital architecture (CASTLE) is accurate but slower than the analog CNN-UMs. It is generally disadvantageous especially if transient computing is critical. The operation speed of the emulated digital implementations, namely CASTLE, can be increased significantly using the pipeline technique. This solution is analyzed with respect to area, time, etc. These arithmetic cores were tested and simulated using a VIRTEX FPGA development system.

Open Access: Yes

DOI: 10.1109/CNNA.2002.1035070