The paper introduces a new way for teaching of delay insensitive asynchronous logic circuits. The studies start on high level models, which are VHDL implementations of Dennis-type static dataflow systems. Investigating the operation of the concurrent processes of these models, the main elements of the delay insensitive systems can be derived. Introducing constant weight 'm-of-n' codes immediately at the beginning of the course leads to a proper generalization. So the well known dual-rail code circuits can be considered as special cases of the constant weight code delay insensitive circuits. The paper presents briefly the design practice sessions for students. © 2011 IEEE.